XCV1000-4BGG560C- Virtex XILINX FPGA IC XCV50 XCV150 XCV100 XCV200 XCV300 XCV400 XCV1000

Virtex series XILINX FPGA families XCV50 XCV150 XCV100 XCV200 XCV300 XCV400 XCV1000 XCV800 ICs Obsolete XCV1000-4BGG560

Virtex series XILINX FPGA families ICs Obsolete XCV1000-4BGG560C surface mounting FPGA ICs 

XCV50 XCV150 XCV100 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000

Features:

Fast, high-density Field Programmable Gate Arrays - Densities from 50k to 1M system gates - System performance up to 200 MHz - 66-MHz PCI Compliant - Hot-swappable for Compact PCI • Multi-standard SelectIO™ interfaces - 16 high-performance interface standards - Connects directly to ZBTRAM devices • Built-in clock-management circuitry - Four dedicated delay-locked loops (DLLs) for advanced clock control - Four primary low-skew global clock distribution nets, plus 24 secondary local clock nets • Hierarchical memory system - LUTs configurable as 16-bit RAM, 32-bit RAM, 16-bit dual-ported RAM, or 16-bit Shift Register - Configurable synchronous dual-ported 4k-bit RAMs - Fast interfaces to external high-performance RAMs • Flexible architecture that balances speed and density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode • Supported by FPGA Foundation™ and Alliance Development Systems - Complete support for Unified Libraries, Relationally Placed Macros, and Design Manager - Wide selection of PC and workstation platforms • SRAM-based in-system configuration - Unlimited re-programmability - Four programming modes • 0.22 μm 5-layer metal process • 100% factory tested.

Specification:

XILINX Virtex™ 2.5 V Field Programmable Gate Arrays FPGA Families Data Sheet(Some Product are Obsolete/Under Obsolescence,welcome to contact us by ic@icschip.com for more information)

Introduction :

Description :

The Virtex FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 5-layer-metal 0.22 μm CMOS process. These advances make Virtex FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex family comprises the nine members shown in Table 1. Building on experience gained from previous generations of FPGAs, the Virtex family represents a revolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.

The Spartan® and the Spartan-XL FPGA families are a high-volume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates. These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume, approach and in many cases are equivalent to mask programmed ASIC devices. By streamlining the Spartan series feature set, leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spartan and Spartan-XL families in the Spartan series have ten members, as shown in Table 1. Spartan/Spartan-XL FPGA Features Note: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheets for more advanced members for the Spartan Series. • First ASIC replacement FPGA for high-volume production with on-chip RAM • Density up to 1862 logic cells or 40,000 system gates • Streamlined feature set based on XC4000 architecture • System performance beyond 80 MHz • Broad set of AllianceCORE and LogiCORE™ predefined solutions available • Unlimited reprogrammability • Low cost.

System level features - Available in both 5V and 3.3V versions - On-chip SelectRAM™ memory - Fully PCI compliant - Full readback capability for program verification and internal node observability - Dedicated high-speed carry logic - Internal 3-state bus capability - Eight global low-skew clock or signal networks - IEEE 1149.1-compatible Boundary Scan logic - Low cost plastic packages available in all densities - Footprint compatibility in common packages • Fully supported by powerful Xilinx ISE® Classics development system - Fully automatic mapping, placement and routing Additional Spartan-XL Family Features • 3.3V supply for low power with 5V tolerant I/Os • Power down input • Higher performance • Faster carry logic • More flexible high-speed clock network • Latch capability in Configurable Logic Blocks • Input fast capture latch • Optional MUX or 2-input function generator on outputs • 12 mA or 24 mA output drive • 5V and 3.3V PCI compliant • Enhanced Boundary Scan • Express Mode configuration

The Spartan®-3A family of Field-Programmable Gate Arrays (FPGAs) solves the design challenges in most high-volume, cost-sensitive, I/O-intensive electronic applications. The five-member family offers densities ranging from 50,000 to 1.4 million system gates, as shown in Table 1. The Spartan-3A FPGAs are part of the Extended Spartan-3A family, which also include the non-volatile Spartan-3AN and the higher density Spartan-3A DSP FPGAs. The Spartan-3A family builds on the success of the earlier Spartan-3E and Spartan-3 FPGA families. New features improve system performance and reduce the cost of configuration. These Spartan-3A family enhancements, combined with proven 90 nm process technology, deliver more functionality and bandwidth per dollar than ever before, setting the new standard in the programmable logic industry. Because of their exceptionally low cost, Spartan-3A FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection, and digital television equipment. The Spartan-3A family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, lengthy development cycles, and the inherent inflexibility of conventional ASICs, and permit field design upgrades.

Features:

• Very low cost, high-performance logic solution for high-volume, cost-conscious applications

• Dual-range VCCAUX supply simplifies 3.3V-only design

• Suspend, Hibernate modes reduce system power

• Multi-voltage, multi-standard SelectIO™ interface pins

• Up to 502 I/O pins or 227 differential signal pairs

• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O

• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling

• Selectable output drive, up to 24 mA per pin

• QUIETIO standard reduces I/O switching noise

• Full 3.3V ± 10% compatibility and hot swap compliance.

• 640+ Mb/s data transfer rate per differential I/O

• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors

• Enhanced Double Data Rate (DDR) support

• DDR/DDR2 SDRAM support up to 400 Mb/s

• Fully compliant 32-/64-bit, 33/66 MHz PCI® technology support

• Abundant, flexible logic resources • Densities up to 25,344 logic cells, including optional shift register or distributed RAM support

• Efficient wide multiplexers, wide logic

• Fast look-ahead carry logic

• Enhanced 18 x 18 multipliers with optional pipeline

• IEEE 1149.1/1532 JTAG programming/debug port

• Hierarchical SelectRAM™ memory architecture

• Up to 576 Kbits of fast block RAM with byte write enables for processor applications

• Up to 176 Kbits of efficient distributed RAM

• Up to eight Digital Clock Managers (DCMs)

• Clock skew elimination (delay locked loop)

• Frequency synthesis, multiplication, division

• High-resolution phase shifting

• Wide frequency range (5 MHz to over 320 MHz)

• Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing

• Configuration interface to industry-standard PROMs

• Low-cost, space-saving SPI serial Flash PROM

• x8 or x8/x16 BPI parallel NOR Flash PROM

• Low-cost Xilinx® Platform Flash with JTAG

• Unique Device DNA identifier for design authentication

• Load multiple bitstreams under FPGA control

• Post-configuration CRC checking

• Complete Xilinx ISE® and WebPACK™ development system software support plus Spartan-3A Starter Kit

• MicroBlaze™ and PicoBlaze embedded processors

• Low-cost QFP and BGA packaging, Pb-free options

• Common footprints support easy density migration

• Compatible with select Spartan-3AN nonvolatile FPGAs

• Compatible with higher density Spartan-3A DSP FPGAs

• XA Automotive version available

Related products :

Spartan-3A FPGA        Status

XC3S50A               Production

XC3S200A             Production

XC3S400A             Production

XC3S700A             Production

XC3S1400A           Production

XC3S50A –4 Standard Performance VQ100/ VQG100 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C)

XC3S200A –5 High Performance (Commercial only) TQ144/ TQG144 144-pin Thin Quad Flat Pack (TQFP) I Industrial (–40°C to 100°C) XC3S400A FT256/ FTG256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)

XC3S700A FG320/ FGG320 320-ball Fine-Pitch Ball Grid Array (FBGA)

XC3S1400A FG400/ FGG400 400-ball Fine-Pitch Ball Grid Array (FBGA)

XC3S1400A FG484/ FGG484 484-ball Fine-Pitch Ball Grid Array (FBGA)

XC3S1400A  FG676 FGG676 676-ball Fine-Pitch Ball Grid Array (FBGA)

XC3S50(2) 50K 1,728 16 12 192 12K 72K 4 2 124 56

XC3S200(2) 200K 4,320 24 20 480 30K 216K 12 4 173 76

XC3S400(2) 400K 8,064 32 28 896 56K 288K 16 4 264 116

XC3S1000(2) 1M 17,280 48 40 1,920 120K 432K 24 4 391 175

XC3S1500 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221

XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270

XC3S4000 4M 62,208 96 72 6,912 432K 1,728K 96 4 633 300

XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 633 300

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