VSC8254YMR-01 Ethernet ICs TELECOM INTERFACE Network Interfaces Integrated Circuits

VSC8254YMR-01 Ethernet ICs TELECOM INTERFACE 256FCBGA Network Interfaces Integrated Circuits

Application:

Target applications for the VSC8254-01 device include switching, IP edge router connectivity, rack mount connectivity through backplane, fiber and copper cable connectivity, and standalone server access (in LAN on motherboard designs or separate network adapters). • Multi-port serial-to-serial signal conditioning with cross-connect • 10GBASE-KR-compliant backplane transceivers • Networks requiring high-accuracy time synchronization • Multi-port XFI/10GBASE-KR to SFI/SFP+ 10 GbE switch cards, router cards, and network adapters In addition, the following MACsec-enabled applications are supported: • Encryption, authentication, and data integrity across external data center interconnections • Secure client and access connections • IEEE 1588 time-stamping on a MACsec port.

Overviews:

The VSC8254-01 device is part of Microsemi’s SynchroPHY™ product family. It is a two channel 1G/10G serial-to-serial Ethernet PHY featuring Microsemi’s VeriTime™ (IEEE 1588v2) precision network timing technology and Intellisec™ (128/256-bit MACsec) encryption. It also supports dual-sided 10GBASE-KR functionality including auto-negotiation and training in a small form factor, low-power FCBGA ideal for a wide array of board-level signal integrity designs and system-level IEEE standard compliant (intelligent) Ethernet connectivity. VeriTime™ is Microsemi’s patent-pending timing technology that delivers the industry’s most accurate IEEE 1588v2 timing implementation. It is the only IEEE 1588v2 solution to be validated by major OEMs in real-world tests and adopted as the preferred low-cost upgrade for meeting emerging requirements in 4G/LTE-Advanced (LTE-A). With its integration of VeriTime, VSC8254-01 delivers the quickest, lowest cost method of implementing the network timing accuracy that is critical in maintaining existing service levels as provider architectures migrate from TDM to packet-based technologies. The VSC8254-01 device supports both 1-step and 2-step PTP frames for ordinary clock, boundary clock, and transparent clock modes of operation, along with complete Y.1731 OAM performance monitoring capabilities. Intellisec™ is Microsemi’s patent-pending flow-based extension of the IEEE 802.1AE-based, end-to-end MACsec solution for confidential communications over any MEF CE 2.0 Ethernet or MPLS service provider connections. It is the world’s first FIPS 197-certified CGM-AES 256-bit strong MACsec, with legacy support for today's CGM-AES 128-bit field deployments. The VSC8254-01 device supports full line rate encryption at both 1 GbE and 10 GbE speeds over multiple media types. The VSC8254-01 device provides a complete suite of on-chip instrumentation including built-in self-test (BIST) functions, line-side and client-side circuit loopbacks, pattern generation, and error detection. Its highly flexible clocking options support LAN and WAN operation using a single 156.25 MHz reference clock rate. Synchronous Ethernet (SyncE) and failover switching for protection routing are also supported. The VSC8254-01 device delivers excellent jitter attenuation with low power. It is well-suited for SFP+ based optical modules and direct-attach copper cabling as well as challenging backplane interface applications.

Telecom IC Ethernet 256-FCBGA (17x17)Specification:

Description:

Interfaces The VSC8254-01 device provides multiple types of interfaces supporting IEEE 802.1ae, IEEE 802.3ae, IEEE 1588v2, and IEEE 802.3ap with hardware-based 10GBASE-KR auto-negotiation and training. The device offers a seamless integration between IEEE 1588v2 and the MACsec engine with no loss of precision. The MACsec functionality in the VSC8254-01 device supports the IEEE 802.1AE 128/256-bit MACsec protocols to meet the security requirements for protecting data traversing Ethernet LANs such as input classification, frame encryption/decryption, performance, and latency monitoring. The device meets the 1 GbE SFP and SFP+ SR/LR/ER/ZR host requirements in accordance with the SFF MSA specifications and compensates for optical impairments in SFP+ applications and degradations of the PCB. The high-speed serial input receiver compensates for loss of optical and copper media performance or margin due to inter-symbol interference (ISI). The high-speed serial transmit output features a 3-tap FIR filter output buffer fully compliant with the 10GBASE-KR standard to provide full 10GBASE-KR support, including 10GBASE-KR state machine, for auto-negotiation and link optimization. The transmit path incorporates a multitap output driver to provide flexibility to meet the demanding 10GBASE-KR (IEEE 802.3ap) Tx output launch requirements. The serial ports support 1.25 Gbps and 10 Gbps modes. Each channel consists of a receiver (Rx) and a transmitter (Tx) subsection. Programmable reference clock inputs (HREFCK LREFCK, and SREFCK) support the modes along with clock and data recovery (CDR) in the Rx and Tx subsections of all channels. Each channel of the device can be in a different mode within the limitations of the available reference clocks, while ensuring the Rx and Tx subsections within a channel are in the same mode.

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