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TMS320C6418ZTS600 TMS320C6416 DSPs Microcontrollers IC MCUs Texas Instrument

Microcontroller IC
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DSP Fixed-Point 32bit 500MHz 4000MIPS 288-Pin FCBGAF28M36x Family Of Devices Is The Second Series In The Concerto Family
C64x Fixed Point DSP - 600MHz, McBSP, 2 X PCI
Electronic Components-Integrated Circuits(IC)
Lead Free Status:
RoHS Compliant, PB Free, Lead Free
New And Original Parts
Operating Temperature:
-40°C ~ 85°C
Surface Mounting
Base Part Number:
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TMS320C6418ZTS600 Microcontroller IC


TMS320C6416 Microcontroller IC


Texas Instrument DSPs IC


Texas Instruments  TMS320C6418ZTS600 TMS320C6416 Microcontrollers IC MCUs Texas Instrument Digital signal processors (DSPs) IC

DSP Fixed-Point 32bit 500MHz 4000MIPS 288-Pin FCBGA




The TMS320C64x™ DSPs (including the TMS320C6418 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6418 (C6418) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 DSP enables customers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting (DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418 device offers cost-effective solutions to high-performance DSP programming challenges. The C6418 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The C6418 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6418 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.
The C6418 device has a high-performance embedded coprocessor [Viterbi Decoder Coprocessor (VCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP and the CPU are carried out through the EDMA controller.
The C6418 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache (up to 256K bytes), or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.
Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6418 has sufficient bandwidth to support all six serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.
McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.
The I2C ports on the TMS320C6418 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.


  • Specifications:
Category Integrated Circuits (ICs)
  Microcontrollers IC
Mfr Texas Instruments
Series MCU ICs
Package Tray & Reel (TR)
Part Status Active
Main Purpose General purpose
Operating Temperature -40°C ~ 85°C
Mounting Type Surface Mount
Package / Case BGA/QFP
Product Number TMS320C6418 TMS320C6421
DSP 1 C64x
DSP MHz (Max) 600
CPU 32-/64-bit
Operating system DSP/BIOS
Rating Catalog
Operating temperature range (C) -40 to 105, 0 to 90


Features for the TMS320C64:


High-Performance Fixed-Point Digital Signal Processor (TMS320C6418)
Commercial Temperature Device
1.67-ns Instruction Cycle Time
600-MHz Clock Rate
4800 MIPS
Extended Temperature Device
2-ns Instruction Cycle Time
500-MHz Clock Rate
4000 MIPS
Eight 32-Bit Instructions/Cycle
Fully Software-Compatible With C64x™
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
Load-Store Architecture With Non-Aligned Support
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection
Bit-Field Extract, Set, Clear
Normalization, Saturation, Bit-Counting
VelociTI.2™ Increased Orthogonality
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
Viterbi Decoder Coprocessor (VCP)
Supports Over 500 7.95-Kbps AMR
Programmable Code Parameters
L1/L2 Memory Architecture
128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
4M-Bit (512K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
Endianess: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
512M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
Host-Port Interface (HPI) [32-/16-Bit]
Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
Two Inter-Integrated Circuit (I2C) Buses
Additional GPIO Capability
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Sixteen General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
On-Chip Fundamental Oscillator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/Os, 1.4-V Internal (-600)
3.3-V I/Os, 1.2-V Internal (A-500)

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TMS320C5533 TMS320C5533AZAYA10 SMJ320VC5416
TMS320C5534 TMS320C5534AZAY05 SMV320C6727B-SP
TMS320C5534 TMS320C5534AZAY10 SMV320C6727B-SP
TMS320C5534 TMS320C5534AZAYA05 TAS3103A
TMS320C5534 TMS320C5534AZAYA10 TAS3108
TMS320C5535 TMS320C5535AZAY05 TAS3202
TMS320C5535 TMS320C5535AZAY10 TAS3204
TMS320C5535 TMS320C5535AZAYA05 TAS3204
TMS320C5535 TMS320C5535AZAYA10 TMS320C6203BGNY173
TMS320C6202B TMS32C6202BGNZA250 TMS320C6203BGNY300
TMS320C6202B TMS320C6202BGNY250 TMS320C6203BZNY300
TMS320C6203B TMS320C6202BZNZ300 TMS32C6203BGNZA250
TMS320C6204 TMS320C6204GWTA200 TMS320C6204ZWTA200
TMS320C6204 TMS320C6204ZWT200 TMS320C6205DZWT200
TMS320C6414TBCLZ6 TMS320C6205DGWT200 TMS320C6205GWT200
TMS320C6205 TMS32C6205DGWTA200 TMS320C6205GWTA200
TMS320C6205 TMS32C6205DZWTA200 TMS320C6205ZWT200
TMS320C6211B TMS320C6211BGFN150 TMS32C6211BZFNA150
TMS320C6416TBCLZA7 TMS320C6211BZFN167 TMS320C6410ZTS400
TMS320C6410 TMS320C6410GTS400 TMS320C6410ZTSA400
TMS320C6412 TMS320C6412AGDK5 TMS320C6412AZNZ6
TMS320C6412AZDK7 TMS320C6412AGDK7 TMS320C6412AZNZ7
TMS320C6412AZNZ5 TMS320C6412AGNZ5 TMS320C6412AGNZ6
TMS320C6412AZDK6 TMS320C6412AGNZ7 TMS320C6412AGDK6
TMS320C6412 TMS320C6412AGNZA5 TMS320C6412AGNZA6
TMS320C6413 TMS320C6413GTS500 TMS320C6413ZTS500
TMS320C6414TBGLZ6 TMS320C6413GTSA500 TMS320C6413ZTSA500
TMS320C6414 TMS32C6414EGLZA5E0 TMS320C6414TBGLZ7
TMS320C6415 TMS32C6415EGLZA5E0 TMS320C6415TBGLZ6
TMS320C6415T TMS320C6415TBCLZ1 TMS320C6415TBGLZA8
TMS320C6416 TMS32C6416EGLZ7E3 TMS32C6416EGLZA6E3
TMS320C6416T TMS320C6416TBCLZ7 TMS320C6416TBCLZ1
TMS320C6416TBCLZD1 TMS320C6416TBCLZA6 TMS320C6418GTS600
TMS320C6418 TMS320C6418GTSA500 TMS320C6418ZTSA500
TMS320C6418 TMS320C6418ZTS600 TMS320C6421ZDU4
TMS320C6421 TMS320C6421ZDU7 TMS320C6421ZDUL
TMS320C6421 TMS320C6421ZWT4 TMS320C6421ZWT5

Environmental & Export Classifications:

RoHS Status ROHS3 Compliant
Moisture Sensitivity Level (MSL) 3 (168 Hours)
REACH Status REACH Unaffected
HTSUS 8542.39.0001


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