XC2C256-6PQG208C XC2C256-7CPG132C XC2C256-7CPG132I XC2C256-7TQG144C XC2C256-7TQG144I XC2C256-7VQG100C XC2C256-7VQG100I
XC2C256-6PQG208C XC2C256-7CPG132C XC2C256-7CPG132I XC2C256-7TQG144C XC2C256-7TQG144I XC2C256-7VQG100C XC2C256-7VQG100I
XC2C256 XILINX FLASH PLD, 6NS, 256-CELL, PLA-TYPE, CMOS, PQFP208 ICs
| Category | Integrated Circuits (ICs) |
| Family | Embedded - FPGAs (Field Programmable Gate Array) |
| Mfr | Xilinx Inc. |
| Series | XC2C256 XILINX FLASH PLD, 6NS, 256-CELL, PLA-TYPE, CMOS, PQFP208 ICs |
| Base Product Number | XC2C256-6PQG208C XC2C256-7CPG132C XC2C256-7CPG132I XC2C256-7TQG144C XC2C256-7TQG144I XC2C256-7VQG100C XC2C256-7VQG100I |
Features:
• Very low cost, high-performance logic solution for high-volume, cost-conscious applications
• Dual-range VCCAUX supply simplifies 3.3V-only design
• Suspend, Hibernate modes reduce system power
• Multi-voltage, multi-standard SelectIO™ interface pins
• Up to 502 I/O pins or 227 differential signal pairs
• LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
• 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
• Selectable output drive, up to 24 mA per pin
• QUIETIO standard reduces I/O switching noise
• Full 3.3V ± 10% compatibility and hot swap compliance.
• 640+ Mb/s data transfer rate per differential I/O
• LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with integrated differential termination resistors
• Enhanced Double Data Rate (DDR) support
• DDR/DDR2 SDRAM support up to 400 Mb/s
• Fully compliant 32-/64-bit, 33/66 MHz PCI® technology support
• Abundant, flexible logic resources • Densities up to 25,344 logic cells, including optional shift register or distributed RAM support
• Efficient wide multiplexers, wide logic
• Fast look-ahead carry logic
• Enhanced 18 x 18 multipliers with optional pipeline
• IEEE 1149.1/1532 JTAG programming/debug port
• Hierarchical SelectRAM™ memory architecture
• Up to 576 Kbits of fast block RAM with byte write enables for processor applications
• Up to 176 Kbits of efficient distributed RAM
• Up to eight Digital Clock Managers (DCMs)
• Clock skew elimination (delay locked loop)
• Frequency synthesis, multiplication, division
• High-resolution phase shifting
• Wide frequency range (5 MHz to over 320 MHz)
• Eight low-skew global clock networks, eight additional clocks per half device, plus abundant low-skew routing
• Configuration interface to industry-standard PROMs
• Low-cost, space-saving SPI serial Flash PROM
• x8 or x8/x16 BPI parallel NOR Flash PROM
• Low-cost Xilinx® Platform Flash with JTAG
• Unique Device DNA identifier for design authentication
• Load multiple bitstreams under FPGA control
• Post-configuration CRC checking
• Complete Xilinx ISE® and WebPACK™ development system software support plus Spartan-3A Starter Kit
• MicroBlaze™ and PicoBlaze embedded processors
• Low-cost QFP and BGA packaging, Pb-free options
• Common footprints support easy density migration
• Compatible with select Spartan-3AN nonvolatile FPGAs
• Compatible with higher density Spartan-3A DSP FPGAs
• XA Automotive version available
Related products :
Spartan-3A FPGA Status
XC3S50A Production
XC3S200A Production
XC3S400A Production
XC3S700A Production
XC3S1400A Production
XC3S50A –4 Standard Performance VQ100/ VQG100 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0°C to 85°C)
XC3S200A –5 High Performance (Commercial only) TQ144/ TQG144 144-pin Thin Quad Flat Pack (TQFP) I Industrial (–40°C to 100°C) XC3S400A FT256/ FTG256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)
XC3S700A FG320/ FGG320 320-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S1400A FG400/ FGG400 400-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S1400A FG484/ FGG484 484-ball Fine-Pitch Ball Grid Array (FBGA)
XC3S1400A FG676 FGG676 676-ball Fine-Pitch Ball Grid Array (FBGA)
For more information on stock availability of the Spartan-3A FPGA family,Please feel free to send email : ic@icschip.com
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